Risky Chips

CSL Team Probes the Rising Risk of Latch-up

By Doug Peterson

September 2007

It can begin with a glitch.

Perhaps it starts with a pulse on one of the power supply lines in an integrated circuit. This pulse can trigger a parasitic device to turn on somewhere in the circuitry, creating a low-resistance pathway between the power supply and the ground. Current starts to flow and the chip burns up.

This problem goes under the innocuous-sounding name of “latch-up,” but it’s a long-standing, serious problem in the world of integrated circuits. CSL researchers are studying the latch-up process, trying to understand it better and model it. The ultimate goal is to develop circuit-level models that can determine whether a particular chip will or will not have a latch-up problem, says CSL professor Elyse Rosenbaum.

Epi Wafers and Latch-up

According to Rosenbaum, the latch-up problem has been on the rise ever since the IC industry started moving away from using epitaxial wafers, or Epi wafers, as the substrate for chips.

“Epi wafers use a very low-resistivity substrate,” she explains. “And it’s very hard to trigger latch-up when you have a low-resistivity substrate.”

However, she says, Epi-wafer substrates are more expensive and not as effective when you are building radio frequency integrated circuits. This has spurred the move away from Epi wafers, boosting the risk of latch-up.

Another factor has been the demand by manufacturers for transient voltage suppressors built into the chip. Normally, transient voltage suppressors have been built into the circuit board to take care of system-level electrostatic discharge (ESD) problems. But by building them into the chip, the risk of latch-up increases.

ESD Protection

In addition to latch-up research, Rosenbaum’s group is nationally known for its work on ESD protection, which prevents circuits from being cooked by electrostatic discharges.

Static charge is created whenever two objects made from dissimilar materials come into contact and then separate. If a charged-up object comes near a grounded conductor, current flows briefly and the charge is dissipated. For instance, you create a charge when you scuff your feet on a carpet; the discharge occurs when you touch a doorknob, causing current to flow from your body to the ground. But what appears to be a harmless discharge to a human can wreak havoc if it passes through circuits with components smaller than a speck of dust.

“Can you imagine that charge going through something that is less than one-millionth of a meter?” Rosenbaum asks. “The current intensity is so high that it causes melting in an integrated circuit.

“It’s not a problem that can go away,” she adds. “It’s the basic physics of the world around us.” In fact, as devices get smaller, the ESD problem only gets bigger.

CDM Stress

Rosenbaum points out that there is very little human handling of chips, so electrostatic discharges are most likely to be created during machine handling, causing charged-device model stress, or CDM stress.

“The industry does failure analysis when customers return parts,” she says, “and the signature of most failures today is CDM stress.”

Rosenbaum’s team is one of the best academic groups in the country when it comes to designing ESD-protection circuitry. It is a difficult process, she says, particularly with chips that operate at gigabits or multi-gigabits per second. At those speeds, the ESD circuitry can attenuate the incoming signals, but her team makes the ESD circuitry small enough to lower that effect.

Rosenbaum’s team specializes in co-design, in which they design the active circuitry and the ESD protection circuitry at the same time.

“That way,” she says, “the system as a whole is able to meet both reliability and performance specifications.”

The bottom line: The chip will be both fast and reliable.

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