Research Project Title
ESD Protection Methods for Submicron Analog and RF Integrated Circuits

Principal Investigators
Elyse Rosenbaum

Unit #3
Project Overview

This project designs, tests, models, and simulates ESD protection circuits for submicron analog and RF integrated circuits.

We have designed ESD protection devices and circuits; these are fabricated on test wafers using Motorola's RF BiCMOS technology (Si and SiGe), with many of the circuits now being included in a variety of Motorola design libraries. For example, the replacement of the resistor in the classic Zener-triggered bipolar ESD protection circuit with NMOS device improves protection levels while decreasing its parasitic leakage current. Motorola's BiCMOS technology also has an option for creating NMOS transistors inside an isolated p-well. We have demonstrated that if the body terminal of these devices is left floating, they provide very good ESD protection.

Through rigorous analysis, we have explained why the Zener-triggered bipolar ESD protection circuit may not enter the protection regime at the trigger diode breakdown voltage, and as a result have derived general conditions for collector breakdown of a BJT with finite base resistance.

We are developing a circuit-level simulation model for the bipolar ESD protection device. This model can be implemented in any circuit simulator, as it will be written in a language such as VerilogA, which can be interpreted by a variety of tools, such as Cadence's Spectre and Motorola's own proprietary simulator, Mica. The model may need to account for non-quasi-static phenomena, which may entail the use of our very-fast transmission line pulsing (VFTLP) system for the necessary measurement data.